特殊的輸入/輸出指令
I/O端口映射與桌面系統(tǒng)一樣，3BHE022886R0001包括特殊的輸入/輸出指令，用于訪問I/O尋址空間中的I/O外圍設(shè)備（與內(nèi)存尋址空間分離且不同）。I/O地址空間中的位置稱為端口。當(dāng)CPU解碼并執(zhí)行I/O指令時，它在線A00至A15上產(chǎn)生一個16位I/O地址，并用M/I/O控制線識別I/O周期。因此，CPU包括一個獨立的64KB I/O地址空間，可作為字節(jié)、字或長字訪問。標(biāo)準(zhǔn)硬件電路僅為外圍設(shè)備保留1024字節(jié)的I/O尋址空間，從I/O$000到$3FF。所有標(biāo)準(zhǔn)的PC I/O外圍設(shè)備，如串行和并行端口、硬盤和軟盤驅(qū)動器控制器、視頻系統(tǒng)、實時時鐘、系統(tǒng)計時器和中斷控制器都在I/O空間的這一區(qū)域中進行處理。BIOS正確初始化和配置所有這些寄存器；通常不需要直接調(diào)整這些I/O端口。分配的和用戶可用的I/O地址匯總在I/O地址中
單獨的硬件中斷線分配
系統(tǒng)中斷除了I/O端口地址外，I/O設(shè)備還具有單獨的硬件中斷線分配。分配給每個中斷行的是存儲器中$00000到$003FF的256矢量中斷表中的相應(yīng)中斷矢量。列出了16個可屏蔽中斷和單個不可屏蔽中斷（NMI）及其功能。詳細說明了中斷向量表中的向量。也為實模式和保護模式定義了十六進制和十進制的中斷數(shù)。3BHE022886R0001上的中斷硬件實現(xiàn)是基于PC架構(gòu)（從IBM PC/XT演變而來）構(gòu)建的計算機的標(biāo)準(zhǔn)。在IBM PC/XT計算機中，只有八條中斷請求線存在，在PIC上編號為IRQ0到IRQ7。IBM PC/AT計算機通過將第二個從PIC級聯(lián)到原始主PIC中，又增加了八條IRQx線，編號為IRQ8到IRQ15。主PIC處的IRQ2被提交作為從PIC的級聯(lián)輸入。
Special input/output instructions
Like desktop systems, 3BHE022886R0001 includes special I/O instructions for accessing I/O peripherals in the I/O addressing space (separate from and different from the memory addressing space). The location in the I/O address space is called a port. When the CPU decodes and executes the I/O instruction, it generates a 16 bit I/O address from A00 to A15, and uses the M/I/O control line to identify the I/O cycle. Therefore, the CPU includes an independent 64KB I/O address space that can be accessed as bytes, words, or long words. The standard hardware circuit only reserves 1024 bytes of I/O addressing space for peripheral devices, from I/O $000 to $3FF. All standard PC I/O peripherals, such as serial and parallel ports, hard disk and floppy disk drive controllers, video systems, real-time clocks, system timers, and interrupt controllers, are processed in this area of the I/O space. BIOS correctly initializes and configures all these registers; These I/O ports usually do not need to be adjusted directly. Allocated and user available I/O addresses are summarized in I/O addresses
Disconnection allocation in separate hardware
In addition to the I/O port address, the I/O device also has separate hardware disconnection allocation. Each interrupt row is assigned the corresponding interrupt vector in the 256 vector interrupt table of $00000 to $003FF in memory. The 16 maskable interrupts and a single non maskable interrupt (NMI) and their functions are listed. The vectors in the interrupt vector table are described in detail. Hexadecimal and decimal interrupt numbers are also defined for real mode and protected mode. The interrupt hardware implementation on 3BHE022886R0001 is a computer standard based on PC architecture (evolved from IBM PC/XT). In the IBM PC/XT computer, only eight interrupt request lines exist, numbered IRQ0 to IRQ7 on the PIC. By cascading the second PIC to the original main PIC, the IBM PC/AT computer adds eight IRQ x-rays, numbered IRQ8 to IRQ15. IRQ2 at the master PIC is submitted as a cascading input to the slave PIC.
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