DSDI146以太網(wǎng)模塊
FBC存儲器的離散和模擬輸入數(shù)據(jù)區(qū)域FBC雙端口存儲器的該區(qū)域包含每個(gè)配置的輸入應(yīng)用傳輸變量（TVA）。FIP總線控制器將消耗的數(shù)據(jù)TVA（包括狀態(tài)、抖動(dòng)和專用報(bào)警數(shù)據(jù)）直接放入其存儲器的I/O數(shù)據(jù)區(qū)。這是隨后將映射到PLC的%I和%AI參考表的數(shù)據(jù)。如果數(shù)據(jù)TVA不能從網(wǎng)絡(luò)中消耗，通常由于缺乏及時(shí)性或刷新，F(xiàn)IP總線控制器根據(jù)其配置默認(rèn)數(shù)據(jù)（為0或保持其最后狀態(tài)）。FBC存儲器的輸入點(diǎn)故障觸點(diǎn)和報(bào)警數(shù)據(jù)區(qū)域該區(qū)域包含與輸入數(shù)據(jù)相關(guān)的驗(yàn)證程序TVA。PLC使用驗(yàn)證器信息驅(qū)動(dòng)與離散點(diǎn)和模擬通道相關(guān)的點(diǎn)故障觸點(diǎn)的狀態(tài)。PLC還使用該信息驅(qū)動(dòng)與一些模擬輸入相關(guān)的任何高報(bào)警觸點(diǎn)和低報(bào)警觸點(diǎn)。每個(gè)離散輸入位都有一個(gè)位點(diǎn)故障觸點(diǎn)。每個(gè)模擬輸入通道都有一個(gè)包含點(diǎn)故障和報(bào)警故障觸點(diǎn)的單字節(jié)。FIP總線控制器將成功消費(fèi)的驗(yàn)證程序TVA放置在此區(qū)域，無需修改。如果驗(yàn)證器TVA無法使用，通常由于缺乏及時(shí)性或更新，F(xiàn)BC僅設(shè)置影響離散和模擬數(shù)據(jù)點(diǎn)故障觸點(diǎn)的位。模擬TVA的剩余位保持其最后狀態(tài)。因此，如果設(shè)置了任何報(bào)警觸點(diǎn)位，則如果驗(yàn)證程序TVA不再被使用，則保持設(shè)置。FBC存儲器的離散和模擬輸出數(shù)據(jù)區(qū)該FBC存儲器區(qū)域包含每個(gè)配置的輸出應(yīng)用傳輸變量（TVA）。CPU將輸出數(shù)據(jù)（包括PLC的%Q和%AQ參考表中的狀態(tài)和閃爍數(shù)據(jù)）放入該區(qū)域。當(dāng)FBC檢測到新的輸出數(shù)據(jù)時(shí)，它將數(shù)據(jù)直接復(fù)制到一個(gè)或多個(gè)COMV中，并在FIP網(wǎng)絡(luò)上生成每個(gè)COMV。如果FIP總線控制器沒有從PLC CPU接收到新數(shù)據(jù)，則不會刷新COMV。然后，基于配置的刷新定時(shí)器，COMV可以變?yōu)槲此⑿?。FIP總線控制器掃描進(jìn)出FIP網(wǎng)絡(luò)的I/O數(shù)據(jù)。在FIP網(wǎng)絡(luò)上，每個(gè)I/O數(shù)據(jù)TVA被分配給一個(gè)時(shí)隙。
時(shí)隙是在指定時(shí)段發(fā)生的FIP宏周期的特定段。
在PLC CPU中，每個(gè)時(shí)隙必須與一個(gè)CPU掃描集相關(guān)聯(lián)。一個(gè)或多個(gè)時(shí)隙可以包括在同一掃描集中。
在FIP網(wǎng)絡(luò)上，分配給同一時(shí)隙的I/O數(shù)據(jù)TVA被合并到通信變量（COMV）。然后在FIP上轉(zhuǎn)移COMV在為TVA定義的同一時(shí)隙中的網(wǎng)絡(luò)。
異步或同步網(wǎng)絡(luò)訪問FBC提供兩種網(wǎng)絡(luò)訪問方法，異步和同步。使用哪種方法取決于PLC應(yīng)用的需要
程序。如果應(yīng)用程序必須與實(shí)際在FIP網(wǎng)絡(luò)上生成數(shù)據(jù)時(shí)，同步掃描方法必須使用。在所有其他情況下，異步網(wǎng)絡(luò)訪問方法可能是更可取
Discrete and Analog Input Data Area of FBC Memory This area of the FBC’s dual-port memory contains each configured input application transfer variable (TVA). The FIP Bus Controller places consumed data TVAs, including state, chatter, and specialized alarm data, directly into this I/O data area of its memory. This is the data that will subsequently be mapped to the PLC’s %I and %AI reference tables. If a data TVA cannot be consumed from the network, usually for lack of promptness or refreshment, the FIP Bus Controller defaults the data (to 0 or to hold its last state) according to its configuration. Input Point Fault Contacts and Alarm Data Area of FBC Memory This area contains validator TVAs associated with input data. The PLC uses validator information to drive the states of point fault contacts associated with discrete points and analog channels. The PLC also uses this information to drive any high and low alarm contacts associated with some analog inputs. There is a bit point fault contact for each discrete input bit. A single byte containing the point fault and alarm fault contacts is present for each analog input channel. The FIP Bus Controller places successfully consumed validator TVAs in this area without modification. If a validator TVA cannot be consumed, usually for lack of promptness or refreshment, the FBC sets only the bit that affects the point fault contact for the discrete and analog data. The remaining bits of the analog TVA hold their last state. Therefore, if any alarm contact bit is set, it remains set if the validator TVA can no longer be consumed. Discrete and Analog Output Data Area of FBC Memory This area of FBC memory contains each configured output application transfer variable (TVA). The CPU places the output data, including state and blink data from the PLC’s %Q and %AQ reference table into this area. When the FBC detects new output data, it copies the data directly into one or more COMVs and produces each COMV on the FIP network. If the FIP Bus Controller does not receive new data from the PLC CPU, it does not refresh the COMV. The COMV may then become unrefreshed based on the configured refreshment timers.The FIP Bus Controller scans I/O data to and from the FIP network. On the FIP network,
each I/O data TVA is assigned to a time slot.
Time Slots
A time slot is a specific segment of the FIP macrocycle that occurs at a designated period.
In the PLC CPU, each time slot must be associated with one of the CPU scan sets. One
or more time slots may be included in the same scan set.
On the FIP network, I/O data TVAs assigned to the same time slot are combined into
Communication Variables (COMVs). The COMVs are then transferred on the FIP
network in the same time slot that was defined for the TVAs.
Asynchronous or Synchronous Network Access
The FBC provides two methods of Network Access, asynchronous and synchronous.
The choice of which method to use depends on the needs of the PLC application
program(s). If the application program must be synchronized with the actual
production of the data on the FIP network, then the synchronous scanning method must
be used. In all other cases, the asynchronous Network Access method is probably
preferable.
