3BHE023784R1023使用產(chǎn)品，ABB控制模塊
數(shù)據(jù)傳輸說明VMIVME-2511通過連接器P3和P4執(zhí)行輸入/輸出傳輸，這是可從卡的正面訪問。輸入/輸出傳輸通過端口實(shí)現(xiàn)在板上注冊所需的PliT模塊。使用可選緩沖器，110操作當(dāng)可選輸出緩沖時(shí)，VMIVME-2511是Pl/T模塊的子集使用。這種情況是由于八進(jìn)制收發(fā)器用于將數(shù)據(jù)緩沖到和從PIIT的每個(gè)輸入/輸出端口。雖然該方案將PI/T限制在110可編程性，極大地增強(qiáng)了PIIT操作，具有更大的驅(qū)動(dòng)能力如果不使用緩沖，情況會(huì)更糟。
3BHE023784R1023使用產(chǎn)品PliT編程限制模塊在編程部分進(jìn)行了討論。中斷能力VMIVME-2511能夠處理四個(gè)中斷請求。每個(gè)PIIT模塊能夠發(fā)出兩個(gè)請求，一個(gè)端口中斷請求和一個(gè)定時(shí)器中斷要求四個(gè)中斷請求信號（兩個(gè)來自PIiT#1，兩個(gè)來自PIiT#2）為連接至68153 BIM，為兩個(gè)PIiT模塊提供完全中斷支持。每個(gè)PI/T模塊有兩個(gè)可由用戶編程的板載中斷矢量寄存器。有關(guān)BIM和PI/T模塊中斷的編程見接下來的編程部分。3.5 68230并行接口定時(shí)器68230并行接口和定時(shí)器提供了多功能并行I10與各種外圍設(shè)備和計(jì)算機(jī)系統(tǒng)的接口。每個(gè)8位端口是雙緩沖，每個(gè)端口（端口A和B）有兩條握手線，用于在68230之間有序地傳輸數(shù)據(jù)。見附錄A第12、13和14頁對于端口控制結(jié)構(gòu)，握手定義和I/O接口時(shí)序圖。每個(gè)68230的端口C可用作六條通用I10線路（C0、C1、C4-C7）C2和C3分別用作定時(shí)器時(shí)鐘輸入和定時(shí)器輸出。或者，端口C（C4-C7）可編程為支持68230的中斷結(jié)構(gòu)C2和C3仍然是計(jì)時(shí)器輸入引腳，C0和C1是通用引腳目的110。68230可以通過兩種方式指示服務(wù)需求。處理器可以輪詢端口狀態(tài)寄存器，用于指示握手引腳的狀態(tài)。68230可以是為中斷編程。中斷可能發(fā)生在兩種情況中的任何一種的轉(zhuǎn)換上握手引腳，HI和H2用于端口A，H3和H4用于端口B。這將進(jìn)一步解釋附錄A第15頁。CENTRONICS接口附錄E中提供了質(zhì)心界面的簡單示例互連方案以詳細(xì)的時(shí)序圖顯示。
110 DATA TRANSFER DESCRIPTION
The VMIVME-2511 performs I/O transfers via connectors P3 and P4 which are
accessible from the front of the card. The I/O transfers are achieved through port
registers on board the desired PliT module. With the optional buffers, the 110 operation
of the VMIVME-2511 is a subset of that of the Pl/T module when optional output buffers
are used. This is the case due to the octal transceivers used for buffering data to and
from each of the I/O ports of the PIIT. Although this scheme limits the PI/T in 110
programmability, it greatly enhances the PIIT operation with greater drive capability
than would be the case if buffering were not used. Limitations on programming the PliT
module are discussed in the programming section. INTERRUPT CAPABILITY
The VMIVME-2511 is capable of handling four interrupt requests. Each PIIT
module is capable of two requests, a port interrupt request and a timer interrupt
request. The four interrupt request signals (two from PIiT #1, and two from PIIT #2) are
connected to the 68153 BIM, giving full interrupt support for both PIiT modules. Each
PI/T module has two on-board interrupt vector registers programmable by the user.
Programming concerning interrupts for the BIM and PI/T module are found in the
programming section that follows.
3.5 THE 68230 PARALLEL INTERFACEITIMER
The 68230 Parallel Interface and Timer provides for a versatile parallel I10
interface to a wide variety of peripheral and computer systems. Each 8-bit port is
double buffered and each port (Port A and B) has two handshake lines to provide for
orderly transfer of data to and from the 68230. See Appendix A, pages 12, 13, and 14
for the port control structure, handshaking definition and I/O interface timing diagrams.
Port C of each 68230 may be used as six general purpose I10 lines (C0, C1, C4-C7)
with C2 and C3 used as the timer clock input and timer output, respectively.
Alternatively, port C (C4-C7) may be programmed to support the 68230's interrupt
structure. C2 and C3 remain the timer inputloutput pins, and C0 and C1 are general
purpose 110.
The 68230 may indicate a need for service in two ways. The processor may poll
the Port Status Register to indicate the state of the handshake pins. The 68230 may be
programmed for interrupts. The interrupts may occur on a transition of any of the two
handshake pins, HI and H2 for port A, H3 and H4 for Port B. This is further explained
on page 15 of Appendix A. CENTRONICS INTERFACE
A simple example of a centronic interface is provided in Appendix E. An
interconnection scheme is shown with a detailed timing diagram.
