3BHE025335R1121使用數(shù)據(jù),ABB模塊
ICC計數(shù)器電路由六個部分組成可編程系統(tǒng)定時控制器（STC）。每個STC為ICC提供四個高速計數(shù)器/波形合成接口，提供VMIVME-2540二十四通道數(shù)字信號測量和控制。STC計數(shù)器可能是單獨配置或最多四人一組配置實現(xiàn)各種測量和控制功能。
車載68HC000 CPU配置和管理每個STC直接接口，允許VMEbus主機接口提升到硬件級別以上。訂購選項允許VMIVME-2540出廠配置為1，2、4或6個系統(tǒng)定時控制器。
3BHE025335R1121使用數(shù)據(jù)輸入和系統(tǒng)定時控制器的輸出緩沖在帶有RS-422線路接收器和線路的前面板連接器駕駛員。TTL輸入信號兼容性受將RS-422線路接收器的反向輸入連接到通過前面板的車載1.4 V參考電壓，以及TTL信號傳輸至同相輸入。智能計數(shù)器/控制器的用戶界面由支持的15 MHz 68HC000 CPU實現(xiàn)64 KB的EPROM固件，128 KB的零等待狀態(tài)靜態(tài)RAM，高度集成控制和中斷邏輯。VMEbus主機通過以下方式對ICC進行編程：本地內(nèi)存中的排隊函數(shù)控制塊和發(fā)出命令。CPU通過以下方式響應(yīng)命令：解釋功能控制塊，配置系統(tǒng)定時控制器，然后確認主機命令配置后，CPU將維護數(shù)據(jù)本地存儲器中測量數(shù)據(jù)的結(jié)構(gòu)和測量或控制時中斷VMEbus主機過程已完成。VMIVME-2540的從VMEbus接口在A32中定位64 Kbyte VMEbus本地內(nèi)存窗口或具有DIP開關(guān)的A24地址空間，具有非特權(quán)和/或監(jiān)督訪問。VMEbus主機必須仲裁使用68HC000 CPU進行本地總線訪問，因為RAM是共享的。數(shù)據(jù)訪問可以是D32、D24、D16和D08，并且支持未對齊的傳輸。因為本地CPU從RAM（仲裁器）執(zhí)行其代碼在單一VMEbus數(shù)據(jù)傳輸。
The ICC counter circuitry consists of six
programmable System Timing Controllers (STCs). Each
STC provides the ICC with four high-speed
counter/waveform synthesis interfaces, giving the
VMIVME-2540 twenty-four channels of digital
measurement and control. The STC counters may be
configured individually or in groups of up to four to
implement the various measurement and control functions.
The on-board 68HC000 CPU configures and manages each
STC interface directly, allowing the VMEbus host interface
to be elevated above the hardware level. Ordering options
allow the VMIVME-2540 to be factory configured with 1,
2, 4, or 6 System Timing Controllers. The inputs and
outputs of the System Timing Controllers are buffered at the
front panel connectors with RS-422 line receivers and line
drivers. TTL input signal compatibility is supported by
connecting the inverting input of the RS-422 line receiver to
an on-board 1.4 V reference through the front panel, and the
TTL signal to the noninverting input.
The user interface of the Intelligent Counter/Controller
is implemented by a 15 MHz 68HC000 CPU supported by
64 Kbyte of EPROM firmware, 128 Kbyte of
zero-wait-state static RAM, and highly-integrated control
and interrupt logic. The VMEbus host programs the ICC by
queueing function control blocks in local memory and
issuing commands. The CPU responds to the commands by
interpreting the function control blocks, configuring the
system timing controllers, and then acknowledging the host
command. Once configured, the CPU maintains data
structures of measurement data in local memory and
interrupts the VMEbus host when a measurement or control
process is complete.
The slave VMEbus interface of the VMIVME-2540
locates the 64 Kbyte VMEbus local memory window in A32
or A24 address space with DIP switches, with nonprivileged
and/or Supervisory access. The VMEbus host must arbitrate
with the 68HC000 CPU for local bus access since the RAM
is shared. The data accesses may be D32, D24, D16, and
D08, and unaligned transfers are supported. Because the
local CPU executes its code from RAM, the arbiter
relinquishes control of the local resources after a single
VMEbus data transfer.
