CSA463AE可編程模塊,ABB使用速度
注意，因為FUS LED監(jiān)控多個電壓的狀態(tài)在MVME2603/2604中，它不直接指示狀況任何單個保險絲。如果LED閃爍或熄滅，請檢查所有保險絲（多開關(guān)）。? SYS（DS6，綠色）。系統(tǒng)控制器；當(dāng)宇宙發(fā)光時MVME2603/2604中的ASIC是VMEbus系統(tǒng)控制器。內(nèi)存映射2內(nèi)存映射有三種觀點：? 處理器（MPU總線）查看的所有資源的映射內(nèi)存映射）
? 從PCI本地總線看板載資源的映射主機（PCI總線內(nèi)存映射）
CSA463AE可編程模塊? VMEbus masters查看的車載資源映射（VMEbus內(nèi)存映射）以下各節(jié)對MVME2603/2604進行了概述從以上三個角度來看記憶組織。詳細(xì)的內(nèi)存映射可以在MVME2600系列單板中找到附錄D中列出的《計算機程序員參考指南》，相關(guān)文檔處理器內(nèi)存映射處理器內(nèi)存映射配置由Raven bridge控制器ASIC和Falcon內(nèi)存控制器芯片組。Raven和Falcon設(shè)備調(diào)整系統(tǒng)映射以適應(yīng)給定的通過可編程地圖解碼器寄存器應(yīng)用。系統(tǒng)通電時或者重置，默認(rèn)處理器內(nèi)存映射將接管。默認(rèn)處理器內(nèi)存映射通電或重置時有效的默認(rèn)處理器內(nèi)存映射在針對特定應(yīng)用重新編程之前保持有效。表2-1定義整個默認(rèn)映射（$00000000到$FFFFFFFF）。表2-2進一步定義本地輸入/輸出設(shè)備的映射（可通過PCI/ISA輸入/輸出空間）。筆記1.PCI/ISA輸入/輸出空間的默認(rèn)映射。允許軟件確定系統(tǒng)是基于MPC105還是基于Falcon/Raven檢查PHB設(shè)備ID或CPU類型寄存器。2.ROM/Flash組A的第一個1MB（焊接4MB或8MB）如果ROM\u b\u rvFalcon ROM B基/大小寄存器中的控制位被清除。如果設(shè)置rom_b_rv控制位，該地址范圍映射到只讀存儲器/閃存組B（嵌入1MB只讀存儲器/閃存）。
Note Because the FUS LED monitors the status of several voltages on
the MVME2603/2604, it does not directly indicate the condition
of any single fuse. If the LED flickers or goes out, check all the
fuses (polyswitches).
? SYS (DS6, green). System Controller; lights when the Universe
ASIC in the MVME2603/2604 is the VMEbus system controller.Memory Maps 2
There are three points of view for memory maps:
? The mapping of all resources as viewed by the processor (MPU bus
memory map)
? The mapping of onboard resources as viewed by PCI local bus
masters (PCI bus memory map)
? The mapping of onboard resources as viewed by VMEbus masters
(VMEbus memory map)
The following sections give a general description of the MVME2603/2604
memory organization from the above three points of view. Detailed
memory maps can be found in the MVME2600 Series Single Board
Computer Programmer’s Reference Guide, listed in Appendix D, Related
Documentation.
Processor Memory Map
The processor memory map configuration is under the control of the
Raven bridge controller ASIC and the Falcon memory controller chip set.
The Raven and Falcon devices adjust system mapping to suit a given
application via programmable map decoder registers. At system power-up
or reset, a default processor memory map takes over.Default Processor Memory Map
The default processor memory map that is valid at power-up or reset
remains in effect until reprogrammed for specific applications. Table 2-1
defines the entire default map ($00000000 to $FFFFFFFF). Table 2-2
further defines the map for the local I/O devices (accessible through the
PCI/ISA I/O Space).Notes
1. Default map for PCI/ISA I/O space. Allows software to determine
whether the system is MPC105-based or Falcon/Raven-based by
examining either the PHB Device ID or the CPU Type register.
2. The first 1MB of ROM/Flash bank A (soldered 4MB or 8MB
ROM/Flash) appears in this range after a reset if the rom_b_rv
control bit in the Falcon’s ROM B Base/Size register is cleared. If
the rom_b_rv control bit is set, this address range maps to
ROM/Flash bank B (socketed 1MB ROM/Flash).
