D685A1156U01流量計模塊,ABB中文PDF使用手冊
ROM周期時間可編程為4到11個總線時鐘周期。數(shù)據(jù)傳輸為32位寬。參考單板計算機(jī)程序員參考指南。SCSI傳輸MVME177包括一個SCSI大容量存儲總線接口，具有DMA控制器。SCSI DMA控制器使用FIFO緩沖區(qū)來將8位SCSI總線連接到32位本地總線。FIFO緩沖區(qū)允許SCSI DMA控制器有效地將數(shù)據(jù)傳輸?shù)奖镜乜偩€在四個長單詞突發(fā)。這減少了本地總線使用量SCSI設(shè)備。
D685A1156U01流量計模塊突發(fā)的第一次長字傳輸，禁止監(jiān)聽，要求：? 奇偶校驗(yàn)關(guān)閉的四個總線時鐘，以及? 奇偶校驗(yàn)開啟的五個總線時鐘其余三次傳輸中的每一次都需要一個總線時鐘。DMA控制器在25 MHz時的傳輸速率為44MB/s奇偶校驗(yàn)關(guān)閉。假設(shè)上的連續(xù)傳輸速率為5MB/sSCSI總線的傳輸使用了本地總線帶寬的12%從SCSI總線。LAN DMA傳輸MVME177包括與DMA控制器的LAN接口。這個LAN DMA控制器使用FIFO緩沖區(qū)連接串行LAN總線到32位本地總線。FIFO緩沖區(qū)允許LAN DMA控制器有效地將數(shù)據(jù)傳輸?shù)奖镜乜偩€。82596CA不執(zhí)行MC68060兼容的突發(fā)周期，因此，LAN DMA控制器不使用突發(fā)傳輸。DRAM寫入周期需要3個時鐘周期，讀取周期需要：? 奇偶校驗(yàn)關(guān)閉和? 奇偶校驗(yàn)開啟時的6個時鐘周期LAN DMA控制器的傳輸速率在25時為20MB/sMHz（或30 MHz時為24MB/s），奇偶校驗(yàn)關(guān)閉。假設(shè)LAN總線上的連續(xù)傳輸速率為1MB/s，為局域網(wǎng)總線的傳輸使用本地總線帶寬。遠(yuǎn)程狀態(tài)和控制遠(yuǎn)程狀態(tài)和控制連接器J3是一個20針連接器位于MVME177前面板后面。它提供了系統(tǒng)設(shè)計師可以靈活訪問關(guān)鍵指標(biāo)并重置功能。這允許系統(tǒng)設(shè)計師構(gòu)建重置/中止/LED面板，可從MVME177。除了LED和復(fù)位和中止開關(guān)訪問，該連接器還包括：? 兩個通用TTL級輸入/輸出引腳? 一個通用中斷引腳，也可以作為
觸發(fā)器輸入。該中斷引腳為電平可編程The ROM cycle time is programmable from 4 to 11 bus clock cycles.
The data transfers are 32 bits wide. Refer to the Single Board
Computers Programmer's Reference Guide.
SCSI Transfers
The MVME177 includes a SCSI mass storage bus interface with
DMA controller. The SCSI DMA controller uses a FIFO buffer to
interface the 8-bit SCSI bus to the 32-bit local bus. The FIFO buffer
allows the SCSI DMA controller to efficiently transfer data to the
local bus in four longword bursts. This reduces local bus usage by
the SCSI device.
The first longword transfer of a burst, with snooping disabled,
requires:
? Four bus clocks with parity off, and
? Five bus clocks with parity on
Each of the remaining three transfers requires one bus clock.
The transfer rate of the DMA controller is 44MB/sec at 25 MHz
with parity off. Assuming a continuous transfer rate of 5MB/sec on
the SCSI bus, 12% of the local bus bandwidth is used by transfers
from the SCSI bus. LAN DMA Transfers
The MVME177 includes a LAN interface with DMA controller. The
LAN DMA controller uses a FIFO buffer to interface the serial LAN
bus to the 32-bit local bus. The FIFO buffer allows the LAN DMA
controller to efficiently transfer data to the local bus.
The 82596CA does not execute MC68060 compatible burst cycles,
therefore the LAN DMA controller does not use burst transfers.
DRAM write cycles require 3 clock cycles, and read cycles require:
? 5 clock cycles with parity off and
? 6 clock cycles with parity on
The transfer rate of the LAN DMA controller is 20MB/sec at 25
MHz (or 24MB/sec at 30 MHz) with parity off. Assuming a
continuous transfer rate of 1MB/sec on the LAN bus, 5% (or 4%) of
the local bus bandwidth is used by transfers from the LAN bus.
Remote Status and Control
The remote status and control connector, J3, is a 20-pin connector
located behind the front panel of the MVME177. It provides system
designers the flexibility to access critical indicator and reset
functions. This allows a system designer to construct a
RESET/ABORT/LED panel that can be located remotely from the
MVME177.
In addition to the LED and the RESET and ABORT switches access,
this connector also includes:
? Two general purpose TTL-level I/O pins
? One general purpose interrupt pin which can also function as
a trigger input. This interrupt pin is level programmable
