HONEYWELL 51202329-606連接電纜,51202329-606中文PDF用戶(hù)手冊(cè)
數(shù)據(jù)總線(xiàn)結(jié)構(gòu)MVME162上的本地?cái)?shù)據(jù)總線(xiàn)是基于在MC68040總線(xiàn)上，支持突發(fā)傳輸和偵聽(tīng)。這個(gè)各種本地總線(xiàn)主設(shè)備和從設(shè)備使用本地總線(xiàn)進(jìn)行通信。本地總線(xiàn)由優(yōu)先級(jí)類(lèi)型仲裁器和本地總線(xiàn)的優(yōu)先級(jí)進(jìn)行仲裁總線(xiàn)主機(jī)從高到低依次為：82596CA LAN、NCR 53C710 SCSI、，VMEbus和MPU。一般來(lái)說(shuō)，任何主設(shè)備都可以訪(fǎng)問(wèn)任何從設(shè)備；
HONEYWELL 51202329-606連接電纜然而，并非所有組合都通過(guò)了常識(shí)測(cè)試。請(qǐng)參閱MVME162嵌入式控制器程序員參考指南和用戶(hù)的每個(gè)設(shè)備確定其端口大小、數(shù)據(jù)總線(xiàn)連接和任何訪(fǎng)問(wèn)設(shè)備時(shí)適用的限制。MC68040/MC68LC040微處理器MVME162配備MC68040或MC68LC040微處理器。MC68040/MC68LC040具有片上指令和數(shù)據(jù)緩存；這個(gè)MC68040還提供浮點(diǎn)協(xié)處理器。參見(jiàn)M68040微處理器用戶(hù)手冊(cè)了解更多信息。EPROM和閃存MVME162實(shí)現(xiàn)包括四個(gè)2-Mbit閃存設(shè)備在256Kbit x 8配置中。EPROM位置為標(biāo)準(zhǔn)JEDEC 32-引腳PLCC能夠達(dá)到4Mbit密度（128 Kbit x 8；256 Kbit x 8；512 Kbit x 8；1 Mbit x8）組織為512Kbit x 8設(shè)備。跳線(xiàn)設(shè)置（GPIO3，引腳9-J22上的10）允許從閃存（GPIO3）中提取重置代碼安裝）或從EPROM（GPIO3已卸下）。SRAMMVME162在單個(gè)內(nèi)存中提供512KB的32位寬板載靜態(tài)RAM具有車(chē)載電池備份的非交錯(cuò)架構(gòu)。最壞的情況電池保護(hù)所用時(shí)間為200天。SRAM的詳細(xì)信息性能可在中的SRAM內(nèi)存控制器部分中找到MVME162嵌入式控制器中的MCchip編程模型程序員參考指南。SRAM陣列沒(méi)有奇偶校驗(yàn)保護(hù)。MVME162 SRAM的電池備份功能由Dallas提供DS1210S支持主電源和輔助電源的設(shè)備。在如果主板電源出現(xiàn)故障，DS1210將檢查電源和切換到電壓較高的電源。如果備用電源的電壓低于兩伏，則DS1210會(huì)阻塞第二個(gè)存儲(chǔ)周期；這使軟件能夠向避免數(shù)據(jù)丟失。因?yàn)榈诙卧L(fǎng)問(wèn)可能會(huì)在通電期間被阻止失敗時(shí)，軟件應(yīng)在依賴(lài)數(shù)據(jù)之前至少進(jìn)行兩次訪(fǎng)問(wèn)。MVME162提供跳線(xiàn)（在J20上），允許DS1210通過(guò)引腳連接到VMEbus+5V STDB或連接到車(chē)載電池。例如，主系統(tǒng)備份源可能是蓄電池通過(guò)引腳和二次電源連接到VMEbus+5V STDB可能是車(chē)載電池。如果系統(tǒng)電源出現(xiàn)故障或電路板從機(jī)箱中卸下后，車(chē)載電池將接管。
MC68040/MC68LC040 MPU The MVME162 is equipped with an MC68040 or MC68LC040 microprocessor. The MC68040/MC68LC040 have on-chip instruction and data caches; the MC68040 also provides a floating-point coprocessor. Refer to the M68040 Microprocessor User’s Manual for more information. EPROM and Flash Memory The MVME162 implementation includes four 2-Mbit Flash devices organized in a 256Kbit x 8 configuration. The EPROM location is a standard JEDEC 32- pin PLCC capable of 4 Mbit densities (128 Kbit x 8; 256 Kbit X 8; 512 Kbit x 8; 1 Mbit x8) organized as a 512Kbit x 8 device. A jumper setting (GPIO3, pins 9- 10 on J22) allows reset code to be fetched either from Flash memory (GPIO3 installed) or from the EPROM (GPIO3 removed). SRAM The MVME162 provides 512KB of 32-bit-wide onboard static RAM in a single non-interleaved architecture with onboard battery backup. The worst case elapsed time for battery protection is 200 days. Specifics on SRAM performance can be found in the section on the SRAM Memory Controller in the MCchip Programming Model in the MVME162 Embedded Controller Programmer’s Reference Guide. The SRAM arrays are not parity protected. The battery backup function for the MVME162 SRAM is provided by a Dallas DS1210S device that supports primary and secondary power sources. In the event of a main board power failure, the DS1210S checks power sources and switches to the source with the higher voltage. If the voltage of the backup source is lower than two volts, the DS1210S blocks the second memory cycle; this allows software to provide an early warning to avoid data loss. Because the second access may be blocked during a power failure, software should do at least two accesses before relying on the data. The MVME162 provides jumpers (on J20) that allow either power source of the DS1210S to be connected to the VMEbus +5V STDBY pin or to one cell of the onboard battery. For example, the primary system backup source may be a battery connected to the VMEbus +5V STDBY pin and the secondary source may be the onboard battery. If the system source should fail or the board is removed from the chassis, the onboard battery takes over.
