PFSK151 3BSE018876R1控制板卡，ABB產(chǎn)品尺寸
總線錯(cuò)誤處理由于不同的條件可能導(dǎo)致總線錯(cuò)誤異常，因此軟件必須能夠區(qū)分來(lái)源。為了幫助實(shí)現(xiàn)這一點(diǎn)MVME147在VMEchip和PCC芯片中提供狀態(tài)位。通常，總線錯(cuò)誤處理程序可以查詢(xún)狀態(tài)位和繼續(xù)查看結(jié)果。然而，有兩個(gè)條件會(huì)破壞
狀態(tài)位：? 總線執(zhí)行期間可能發(fā)生中斷錯(cuò)誤處理程序（在指令可以寫(xiě)入狀態(tài)之前寄存器以提升中斷掩碼）。如果中斷服務(wù)例程導(dǎo)致第二個(gè)總線錯(cuò)誤，該狀態(tài)指示第一個(gè)總線錯(cuò)誤的來(lái)源可能丟失。軟件必須為解決這個(gè)問(wèn)題而寫(xiě)。
PFSK151 3BSE018876R1控制板卡PCC可以編程為發(fā)生總線錯(cuò)誤時(shí)，生成7級(jí)中斷。這
當(dāng)總線連接時(shí)，可能有助于將MC68030強(qiáng)制到已知位置出現(xiàn)錯(cuò)誤。
? PCC可以采用VMEbus綁定的BERR*（更新MC68030接收和處理之間的狀態(tài)位）
總線錯(cuò)誤，反之亦然。MC68030執(zhí)行需要不可分割周期的操作序列到本地DRAM和VMEbus。MVME147需要特殊電路來(lái)支持這些操作。不可分割的對(duì)單個(gè)地址的訪問(wèn)稱(chēng)為單地址讀修改寫(xiě)周期（SARMC）。對(duì)多個(gè)地址的不可分割訪問(wèn)稱(chēng)為多地址讀修改寫(xiě)周期（MARMC）。SARMC周期（由測(cè)試和設(shè)置（TA）和單字節(jié)引起比較和交換（CAS）指令）完全受MVME147。這是可能的，因?yàn)閂MEbus定義了這樣的周期。MARMC循環(huán)（由CAS2和多字節(jié)CAS指令引起
和MMU桌面行走）有條件地由MVME147。VMEbus不定義這些周期。PCC中的WAITRMC位控制MARMC的支持周期。如果WAITRMC被清除，則不能保證MARMC循環(huán)不可分割。此外，如果MARMC循環(huán)跨越船上DRAM和VMEbus內(nèi)存，MVME147出現(xiàn)故障。如果設(shè)置了WAITRMC，則保證MARMC循環(huán)是不可分的只有當(dāng)其他VMEbus板實(shí)現(xiàn)其MARMC循環(huán)時(shí)與MVME147相同（帶有WAITRMC集合）。注意，設(shè)置WAITRMC位可能是性能損失。當(dāng)鉆頭設(shè)置后，MVME147等待成為VMEbus主控執(zhí)行任何MARMC循環(huán)（即使它可能只執(zhí)行車(chē)載DRAM）。
Bus Error Processing
Because different conditions can cause bus error exceptions, the
software must be able to distinguish the source. To aid in this, the
MVME147 provides status bits in the VMEchip and PCC chip.
Generally, the bus error handler can interrogate the status bits and
proceed with the result. However, two conditions can corrupt the
status bits:
? An interrupt can happen during the execution of the bus
error handler (before an instruction can write to the status
register to raise the interrupt mask). If the interrupt service
routine causes a second bus error, the status that indicates the
source of the first bus error may be lost. The software must be
written to deal with this. The PCC can be programmed to
generate a Level 7 interrupt when a bus error occurs. This
may help force the MC68030 to a known place when a bus
error occurs.
? The PCC can take a VMEbus bound BERR* (which updates
the status bits) between the MC68030 receiving and handling
of a bus error, or vice-versa. The MC68030 performs operations that require indivisible cycle
sequences to the local DRAM and to the VMEbus. The MVME147
requires special circuitry to support these operations. Indivisible
accesses to a single address are called Single Address Read-ModifyWrite Cycles (SARMC). Indivisible accesses to multiple addresses
are called Multiple Address Read-Modify-Write Cycles (MARMC).
SARMC cycles (caused by Test and Set (TAS) and single byte
Compare and Swap (CAS) instructions) are supported fully by the
MVME147. This is possible because the VMEbus defines such
cycles.
MARMC cycles (caused by CAS2 and multi-byte CAS instructions
and by MMU table walking) are conditionally supported by the
MVME147. The VMEbus does not define these cycles.
The WAITRMC bit in the PCC controls the support of MARMC
cycles. If WAITRMC is cleared, MARMC cycles are not guaranteed
to be indivisible. Furthermore, if MARMC cycles straddle onboard
DRAM and VMEbus memory, the MVME147 malfunctions.
If WAITRMC is set, MARMC cycles are guaranteed to be indivisible
only if the other VMEbus board implements its MARMC cycles the
same way as the MVME147 (with WAITRMC set). Note that setting
the WAITRMC bit can be a performance penalty. When the bit is
set, the MVME147 waits to become VMEbus master before it
