IS200DTAOH1ABA IS210DTAOH1AA燃機模塊，GE使用尺寸
如果VMEbus主機正在執(zhí)行讀-修改-寫循環(huán)（RMC）對于DRAM，GCC多端口仲裁器允許本地總線在讀寫部分之間重新比特序列。然而，它不允許MC68030重新獲得本地總線主控，直到讀寫周期都DRAM發(fā)生。當VMEbus請求本地總線主控和MC68030時是當前本地總線主節(jié)點，它正在執(zhí)行一個循環(huán)需要VMEbus，然后出現(xiàn)雙端口鎖定情況，并且VMEchip通過激活BERR*和HALT*信號線在一起。
IS200DTAOH1ABA IS210DTAOH1AA燃機模塊MC68030通過以下方式響應：中止當前循環(huán)，此時放棄本地總線主控權，以便GCC多端口仲裁器可以將其授予VMEbus。當VMEbus完成DRAM時，GCC多端口仲裁器將本地總線主控權返回給MC68030和它重試已中止的循環(huán)以允許雙端口訪問。
LANCE DRAM訪問當LANCE需要訪問DRAM時，它請求本地總線GCC多端口仲裁器的主控權。獲得批準后LANCE最多執(zhí)行16次DRAM訪問，然后放棄本地總線大師級。如果啟用時發(fā)生奇偶校驗錯誤，則DRAM控制器通過不激活LANRDY*到噴槍來指示。LANCE將此視為內(nèi)存故障，并放棄本地總線Mastership刷新DRAM設備要求其4096/2048/1024行中的每一行每64/32/16毫秒刷新一次。為此，刷新計時器每15微秒請求一次RAM序列器執(zhí)行列地址選通（CAS）之前行地址選通（RAS）刷新周期。
If the VMEbus master is executing a read-modify-write cycle
(RMC) to the DRAM, the GCC multiport arbiter allows rearbitration of the local bus between the read and write portions of
the sequence. It does not, however, allow the MC68030 to regain
local bus mastership until both the read and write cycles have
occurred to the DRAM.
When the VMEbus requests local bus mastership and the MC68030
is the current local bus master and it is executing a cycle that
requires the VMEbus, then a dual port lockup condition occurs and
the VMEchip signals a retry to the MC68030 by activating the
BERR* and HALT* signal lines together. The MC68030 responds by
aborting the current cycle, at which time it relinquishes local bus
mastership so that the GCC multiport arbiter can grant it to the
VMEbus. When the VMEbus has finished with the DRAM, the GCC
multiport arbiter returns local bus mastership to the MC68030 and
it retries the cycle that was aborted to allow the dual port access.
LANCE DRAM Accesses
When the LANCE needs to access DRAM it requests local bus
mastership from the GCC multiport arbiter. When granted, the
LANCE performs up to 16 DRAM accesses, then gives up local bus
mastership. If a parity error occurs while enabled, the DRAM
controller indicates it by not activating LANRDY* to the LANCE.
The LANCE sees this as a memory fault and gives up local bus
mastershipRefresh
The DRAM devices require that each of their 4096/2048/1024 rows
be refreshed once every 64/32/16 milliseconds. To accomplish this,
once every 15 microseconds, the refresh timer requests that the
RAM sequencer perform a Column Address Strobe (CAS) before
Row Address Strobe (RAS) refresh cycle.
