DEIF IOM4.2 2044230041E 2044230040H伺服模塊
WAITRMC控制MVME147的多個(gè)解決RMC（MARMC）循環(huán)。設(shè)置WAITRMC時(shí)MVME147在執(zhí)行之前始終等待VMEbus主控MARMC循環(huán)。如果需要，則應(yīng)設(shè)置WAITRMC保證MARMC循環(huán)的不可分割性（僅當(dāng)其他主機(jī)以與相同的方式實(shí)現(xiàn)MARMC循環(huán)MVME147）。當(dāng)WAITRMC被清除時(shí)，MVME147僅等待VMEbus如果MARMC循環(huán)開始于VMEbus，則為mastership。
DEIF IOM4.2注意，無(wú)論WAITRMC位的狀態(tài)如何，如果MVME147在MARMC，它會(huì)一直保持到MARMC已完成。只有當(dāng)VMEchip中的MASWP位時(shí)，WAITRMC操作才有效清除LCSR（位5$FFFE2005）（禁用MASWP過(guò)帳。）位6-7這些位確定可訪問的本地DRAM部分DMA期間的噴槍。這些位對(duì)生成的中斷級(jí)別進(jìn)行編程。0級(jí)不會(huì)生成中斷。位3當(dāng)該位為高位時(shí)，中斷被啟用。中斷是此位低時(shí)禁用。位7當(dāng)中斷被禁用時(shí)，該位為低，為高當(dāng)中斷被啟用時(shí)。這些位表示PCC的修訂級(jí)別。初始零件釋放為0級(jí)。如果需要在在以后的部分中，修訂級(jí)別將增加。這允許如果功能更改PCC中要求。STAT12表示保險(xiǎn)絲+12V電源的狀態(tài)以太網(wǎng)收發(fā)器電源和串口上拉電源。位1低總是0。當(dāng)打印機(jī)忙時(shí)，位3 BSY為1，不忙時(shí)為0。當(dāng)打印機(jī)處于缺紙狀態(tài)時(shí)，位4 PE為1；當(dāng)打印機(jī)處于缺紙狀態(tài)時(shí)，位4 PE為0事實(shí)并非如此。選擇打印機(jī)時(shí)，位5 SELECT為1，未選擇打印機(jī)時(shí)為0。當(dāng)打印機(jī)處于故障狀態(tài)時(shí)，位6故障為1，當(dāng)打印機(jī)處于故障狀態(tài)時(shí)，位6故障為0
不當(dāng)打印機(jī)確認(rèn)為真時(shí)，位7 ACK為1，否則為0。
WAITRMC controls the MVME147 implementation of multiple
address RMC (MARMC) cycles. When WAITRMC is set, the
MVME147 always waits for VMEbus mastership before executing
an MARMC cycle. WAITRMC should be set if it is desired to
guarantee indivisibility of MARMC cycles (only guaranteed if the
other master implements MARMC cycles the same way as the
MVME147).
When WAITRMC is cleared, the MVME147 only waits for VMEbus
mastership if the MARMC cycle starts out by going to the VMEbus.
Note Regardless of the state of the WAITRMC bit, if the
MVME147 obtains VMEbus mastership during an
MARMC, it maintains it until all of the cycles of
the MARMC are completed.
WAITRMC operation is effective only if MASWP bit in the VMEchip
LCSR (bit 5 $FFFE2005) is cleared (MASWP posting is disabled.)
Bits 6-7 These bits determine the section of local DRAM that is accessible to
the LANCE during DMA. These bits program the interrupt level that is generated. Level 0
does not generate an interrupt.
Bit 3 When this bit is high, the interrupt is enabled. The interrupt is
disabled when this bit is low.
Bit 7 This bit is low when the interrupt is disabled and it is high
when the interrupt is enabled.These bits represent the revision level of the PCC. Initial parts
are released as level 0. If functional changes are required in
future parts, the revision level is incremented. This allows the
software to configure itself should functional changes be
required in the PCC. STAT12 indicates the status of the fused +12V power for
Ethernet transceiver power and for serial port pull up power.
Bit 1 LOW is always 0.
Bit 3 BSY is 1 when the printer is busy and 0 when it is not.
Bit 4 PE is 1 when the printer is in the paper empty state and 0 when
it is not.
Bit 5 SELECT is 1 when the printer is selected and 0 when it is not.
Bit 6 FAULT is 1 when the printer is in the fault state and 0 when it is
not.
