電平敏感
PCI中斷外圍組件互連（PCI）本地總線上的中斷是可選的，并定義為“電平敏感”，使用漏極開路輸出驅(qū)動器斷言為低（負(fù)真）。中斷線INTx#的斷言和反斷言與CLK異步。設(shè)備在請求其設(shè)備驅(qū)動程序注意時斷言其INTx#行。一旦INTx#信號被斷言，它將保持?jǐn)嘌?，直到設(shè)備驅(qū)動程序清除未決請求。當(dāng)請求被清除時，設(shè)備取消斷言其INTx#信號。PCI為單個功能設(shè)備定義了一條中斷線，為多功能設(shè)備或連接器定義了多達四條中斷線。對于單功能設(shè)備，只能使用INTA#，而其他三條中斷線沒有意義。第47頁的圖2-1描述了與VME操作和PMC站點相關(guān)的中斷邏輯。多功能設(shè)備上的任何功能都可以連接到任何INTx#線。中斷引腳寄存器定義函數(shù)用于請求中斷的INTx#線。如果一個設(shè)備實現(xiàn)了一條INTx#線，它被稱為INTA#；如果它實現(xiàn)了兩行，它們被稱為INTA#和INTB#；等等對于多功能設(shè)備，所有功能都可以使用相同的INTx#行，或者每個功能都可以有自己的（最多四個功能），或者它們的任意組合。單個函數(shù)永遠不能在多個INTx#行上生成中斷請求。
PCI設(shè)備中斷映射
從屬PIC通過BIOS定義的線路接受VME中斷。BIOS根據(jù)哪個系統(tǒng)需要使用中斷線來定義要使用的中斷線。PCI設(shè)備中斷映射基于PCI總線的外部設(shè)備包括PMC站點、以太網(wǎng)控制器和PCI到VME橋。默認(rèn)BIOS將這些外部設(shè)備映射到ICH2的PCI中斷請求（PIRQx）線。該映射如圖所示，。無法修改每個設(shè)備上存在的設(shè)備PCI中斷線（INTA到INTD）。
Level sensitive
PCI Interrupt Interrupts Interrupts on the Peripheral Component Interconnect (PCI) local bus are optional and defined as "level sensitive" and asserted as low (negative true) using an open drain output driver. The assertion and anti assertion of interrupt line INTx # are asynchronous with CLK. The device asserts its INTx # line when requesting its device driver attention. Once the INTx # signal is asserted, it will remain asserted until the device driver clears the pending request. When the request is cleared, the device unasserts its INTx # signal. PCI defines one middle break for a single functional device and up to four middle breaks for a multi-function device or connector. For the single function equipment, only INTA # can be used, while the other three medium line breaks are meaningless. Figure 2-1 on page 47 describes the interrupt logic associated with VME operations and PMC sites. Any function on the multi-function device can be connected to any INTx # line. The interrupt pin register defines the INTx # line whose function is used to request interrupts. If a device implements an INTx # line, it is called INTA #; If it implements two lines, they are called INTA # and INTB #; For multi-function devices, all functions can use the same INTx # line, or each function can have its own (up to four functions), or any combination of them. A single function can never generate an interrupt request on multiple INTx # lines.
PCI device interrupt mapping
The slave PIC accepts VME interrupts through the line defined by the BIOS. The BIOS defines the interrupt line to be used according to which system needs to use the interrupt line. PCI device interrupt mapping PCI bus based external devices include PMC sites, Ethernet controllers, and PCI to VME bridges. The default BIOS maps these external devices to the PCI Interrupt Request (PIRQx) line of ICH2. The mapping is shown in the figure,. The device PCI middle line break (INTA to INTD) present on each device cannot be modified.
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