3BHE005555R0101工業(yè)自動化卡件
FSK輸入（現(xiàn)場總線模式）僅適用于現(xiàn)場總線模式下的LDSYN-101工業(yè)自動化卡件，所有數(shù)據(jù)和通信均為共享總線上的FSK編碼數(shù)字信號，需要解碼。微處理器可以通過指定設(shè)備的總線地址來讀取任何輸入。信號通過與多路復(fù)用器和通信電路一起工作的發(fā)送/接收門進(jìn)入FSK通信電路。圖2-3顯示了帶有FSK多路復(fù)用器和FSK發(fā)送/接收門的FSK輸入電路。解碼數(shù)字輸入后，F(xiàn)EC模塊可以將數(shù)據(jù)存儲在存儲器中，或通過I/O擴(kuò)展器總線接口將其直接發(fā)送到控制模塊（MFP/MFC）。FEC模塊可將-10至+10伏范圍內(nèi)的模擬值數(shù)字化。圖2-4顯示了模數(shù)轉(zhuǎn)換電路。模數(shù)控制芯片提供控制雙斜率積分器所需的邏輯。模數(shù)轉(zhuǎn)換分為三個階段：輸入積分、與+10或-10伏參考電壓的去積分以及將積分器/去積分器歸零。微處理器向ADC電路發(fā)出信號，開始轉(zhuǎn)換輸入。ADC電路通過選擇多路復(fù)用器選擇輸入、參考電壓和轉(zhuǎn)換操作。來自選擇多路復(fù)用器的輸入信號通過緩沖器和將輸入信號轉(zhuǎn)換為單端電壓的差分放大器。然后信號到達(dá)積分器/去積分器級的輸入。
I/O擴(kuò)展器總線接口電路
FEC模塊使用半定制門陣列作為I/O擴(kuò)展器總線接口。集成電路（IC）保存所有控制邏輯和通信協(xié)議。該IC電路提供以下功能：?地址比較和檢測。?功能代碼鎖存和解碼。?讀取選通生成。?總線信號的數(shù)據(jù)線濾波。?板載總線驅(qū)動器。ADC電路為該級選擇正或負(fù)參考電壓。一旦積分器設(shè)置為零，ADC電路允許積分器運行，直到其輸出達(dá)到參考電壓。此時，ADC電路選擇去積分操作并開始計數(shù)，直到過零電路檢測到信號為零。反饋和歸零放大器將積分器設(shè)置為零，并且該過程以輸入和參考電壓的相反極性重復(fù)。ADC電路在去積分操作期間進(jìn)行的計數(shù)是輸入的數(shù)字等效值。它將信息和極性發(fā)送給微處理器。微處理器將其放入存儲器，并向ADC電路發(fā)出信號以開始下一次轉(zhuǎn)換。
FSK INPUTS (FIELD BUS MODE)
IMFEC11 ONLY For IMFEC11 modules in the field bus mode, all data and communication are FSK encoded digital signals on a shared bus and require decoding. The microprocessor can read any input by specifying the bus address of the device. The signal enters the FSK communication circuitry through a transmit/receive gate that works with the multiplexer and communication circuitry. Figure 2-3 shows the FSK input circuit with the FSK multiplexer and FSK transmit/receive gate. After decoding the digital input, the FEC module can store that data in memory or send it directly to the controlling module (MFP/MFC) through the I/O expander bus interface.The FEC module can digitize analog values within the range of -10 to +10 volts. Figure 2-4 shows the analog-to-digital conversion circuitry. The analog-to-digital control chip provides the logic needed to control the dual slope integrator. The analog-to-digital conversion takes place in three stages: input integration, de-integration with a +10 or -10 volts reference and zeroing the integrator/de-integrator.The microprocessor signals the ADC circuitry to begin converting inputs. The ADC circuitry selects the input, reference voltage and conversion operation through the select multiplexer. The input signal from the select multiplexer passes through buffers and a differential amplifier that converts the input signal to a single ended voltage. Then the signal goes to the input of the integrator/de-integrator stage.
I/O Expander Bus Interface Circuitry
The FEC module uses a semicustom gate array for the I/O expander bus interface. An integrated circuit (IC) holds all the control logic and communication protocol. This IC circuit provides the following functions: ? Address comparison and detection. ? Function code latching and decoding. ? Read strobe generation. ? Data line filtering of bus signals. ? On-board bus drivers.The ADC circuitry selects a positive or negative reference voltage for this stage. Once the integrator is set to zero, the ADC circuitry allows the integrator to run until its output reaches the reference voltage. At this point, the ADC circuitry selects the de-integration operation and begins a count until the zero crossing circuit detects the signal at zero. A feedback and zeroing amplifier sets the integrator to zero and the process repeats with the opposite polarity of the input and reference voltage. The count that the ADC circuitry takes during the de-integration operation is the digital equivalent of the input. It sends that information and the polarity to the microprocessor. The microprocessor places it into memory and signals the ADC circuitry to begin the next conversion.
