DSDO115A信號輸出模塊
同步I/O掃描
如果需要周期性地處理一組一致的輸入數據，同步I/O需要掃描。可以為FIP定義多達15個同步掃描集總線控制器。
在同步I/O掃描模式下，PLC CPU執(zhí)行同步應用程序
FIP總線控制器完成所有輸入消耗后的程序
同步掃描集中的數據和驗證程序。FIP總線控制器觸發(fā)
PLC CPU和CPU調度指定的應用程序。
PLC CPU掃描PLC參考表中的掃描集輸入，以及程序開始。在邏輯結束時，PLC CPU執(zhí)行輸出掃描（如果已配置）。為了正確操作，程序應完成邏輯并執(zhí)行輸出掃描在FIP總線控制器被調度以產生到網絡的輸出之前。
有關計時的更多詳細信息，請參閱重要產品信息文件，GFK-1200。
下圖顯示了典型同步的定時特性應用在此示例中，單個同步掃描集被配置為包含時隙DI和DO。
離散輸入傳輸時隙：包含輸入的定義傳輸時隙
同步掃描集的數據。允許PLC應用程序的最長時間
輸入時隙被配置在比輸出時隙早但鄰近輸出時隙的相位。
離散輸出傳輸時隙：定義的傳輸時隙，包含同步掃描集的輸出數據。為了允許PLC應用程序的最長時間，輸出時隙配置在比輸入時隙。
FBC消耗延遲：調度消耗之前FBC中的固定延遲
輸入TVAs。該時間固定為1ms。
DI時隙中TVA的FBC消耗：從并將單個TVA傳輸到雙端口存儲器。長度時間取決于COMV和TVA的數量和長度。
Synchronous I/O Scanning
If it is necessary to periodically process a coherent set of input data, synchronous I/O
scanning is required. It is possible to define up to 15 synchronous scan sets for the FIP
Bus Controller.
In Synchronous I/O Scanning mode, the PLC CPU executes a synchronous application
program after the FIP Bus Controller has completed the consumption of all of the input
data and validators in the synchronizing scan set. The FIP Bus Controller triggers the
PLC CPU and the CPU schedules the specified application program.
The PLC CPU scans the scan set inputs into the PLC reference tables, and the program
starts. At the end of the logic the PLC CPU performs the output scan, if one is configured.
For proper operation, the program should complete the logic and perform the output scan
before the FIP Bus Controller is scheduled to produce the outputs to the network.
For more detailed information about timing, please refer to the Important Product
Information document, GFK-1200.
The illustration below represents the timing characteristics of a typical synchronous
application. In this example, a single synchronous scan set is configured to contain the
time slots DI and DO.
Discrete Input Transport Time Slot: The defined transport time slot containing the input
data for the synchronous scan set. To allow the maximum time for the PLC application
program, the input time slot is configured at a phase earlier than but adjacent to the output time slot.
Discrete Output Transport Time Slot: The defined transport time slot containing the
output data for the synchronous scan set. To allow the maximum time for the PLC application program, the output time slot is configured at a phase later than but adjacent to
the input time slot.
FBC Consumption Delay: A fixed delay in the FBC before scheduling the consumption
of the input TVAs. This time is fixed at 1ms.
FBC Consumption of TVAs in DI time slot: The time necessary to read the COMVs from
the network and transfer the individual TVAs to the dual–port memory. The length of
time depends on the number and length of the COMVs and TVAs.
