PPE091A101使用尺寸,ABB控制模塊
如第3.2節(jié)所述，Pl/T模塊的操作可能受到以下限制：八進制緩沖器用于將端口數(shù)據(jù)驅動到P3和P4連接器。此限制限制某些端口模式的使用，例如雙向數(shù)據(jù)傳輸。之前閱讀下一節(jié)，讀者應該了解程序員本手冊附錄中MC68230數(shù)據(jù)規(guī)范的型號部分。用戶還需要閱讀第5.2節(jié)，以確保編程一致在為VMIVME-2511供電之前，使用110個端口的跳線配置。對于關于中斷的編程，讀者應該了解附錄中引用的BIM，用于補充BIM編程描述如下。
PPE091A101使用尺寸4.2 BIM和PIIT寄存器映射MC68153 BIM包含八個8位寄存器，而PI/T模塊分別包含八個8位寄存器包含32個8位寄存器，其中僅使用25個。所有寄存器均位于奇數(shù)字節(jié)位置。BIM寄存器映射如表4-1所示。VMIVME-2511在工廠配置為響應短路監(jiān)控110訪問，但可以配置為通過以下方式響應短期非特權輸入/輸出訪問：安裝跳線，見第5.1節(jié)。在15個地址位A1-A15中，只有8個（A15-A8）被解碼以進行電路板選擇。地址選擇見第5.3節(jié)開關。Pl/T#1寄存器映射如表4-2所示（4頁）。PIIT#2寄存器映射如表4-3（4頁）所示。MC68153 BIM上的八個8位寄存器作為奇數(shù)字節(jié)訪問位置。每個寄存器的位定義可在MC68153 BIM中找到附錄中的規(guī)范。
每個MC68230 Pl/T模塊上的32個8位寄存器訪問如下：奇數(shù)字節(jié)位置。每個寄存器的位定義可以在MC68230中找到PIIT規(guī)范見附錄。編程MC68153 BIM由于Plfr模塊提供它們自己的中斷向量。因此，必須針對外部矢量對BIM進行編程。此外，每個中斷源對應的中斷自動清除位必須為set（高電平）及其相關的中斷啟用位。這將需要每次中斷時用于設置中斷啟用位的中斷服務例程已處理。中斷向量由中斷PIIT模塊在中斷期間提供確認周期。這些矢量由端口中斷矢量寄存器提供并通過PIE模塊上的定時器中斷矢量寄存器，具體取決于正在確認哪個中斷源。
BIM板上的控制寄存器與PllT中斷相關通道如下所示。
As stated in Section 3.2, the operation of the Pl/T module can be limited due to
octal buffers being used to drive port data to the P3 and P4 connectors. This limitation
restricts the use of some port modes, such as bi-directional data transfer. Before
reading the next section the reader should have an understanding of the Programmers
Model section of the MC68230 data specifications in the appendices of this manual.
The user will also want to read Section 5.2 such that the programming is consistent
with the jumper configuration of the 110 ports before powering the VMIVME-2511. For
programming concerning interrupts, the reader should have an understanding of the
BIM which is referenced in the appendices to supplement the BIM programming
description which follows.
4.2 BIM AND PIIT REGISTER MAP
The MC68153 BIM contains eight 8-bit registers while the PI/T modules each
contain 32 eight-bit registers of which only 25 are used. All registers are addressed on
odd-byte locations. The BIM register map is shown in Table 4-1.
The VMIVME-2511 is factory configured to respond to Short Supervisory 110
Access, but can be configured to respond to Short Non-Privileged I/O Access by
installing a jumper, see Section 5.1. Of the 15 address bits A1-A15, only eight
(A15-A8) are decoded for board select. See Section 5.3 for address selection
switches. The Pl/T #1 register map is shown in Table 4-2 (4 pages). The PIIT #2
register map is shown in Table 4-3 (4 pages).
The eight 8-bit registers on board the MC68153 BIM are accessed as odd byte
locations. The bit definition of each register can be found in the MC68153 BIM
specifications in the appendices.
The 32 eight-bit registers on board each MC68230 Pl/T modules are accessed as
odd-byte locations. The bit definition of each register can be found in the MC68230
PIIT specifications in the appendices. PROGRAMMING THE MC68153 BIM
The vector registers on-board the BIM are not used since the Plfr modules supply
their own interrupt vector. Therefore, the BIM must be programmed for external vectors.
In addition, the interrupt auto-clear bit corresponding to each interrupt source must be
set (high level), along with its associated interrupt enable bit. This will require the
interrupt service routine to be used to set the interrupt enable bit each time an interrupt
is processed. The interrupt vector is supplied by the interrupting PIIT module during an interrupt
acknowledge cycle. These vectors are supplied by the Port lnterrupt Vector Register
and by the Timer lnterrupt Vector Register on board the PIE module, depending on
which interrupt source is being acknowledged.
The control registers on-board the BIM are associated with the PllT interrupt
channels as shown below.
