PDD500A101使用流程,ABB處理器
智能計數(shù)器/控制器支持兩個VMEbus中斷器模塊，可斷言兩個模塊中的任何一個同時IRQ水平。檢修時，斷路器模塊以8位中斷向量和自動清除掛起的IRQ。CPU保持內(nèi)存中掛起的中斷事件隊列，寫入新的當(dāng)前一個事件發(fā)生時，中斷器模塊的IRQ變明朗。共模電壓限制：±25 V差模電壓限制：±5 V由于以下原因，差動電壓范圍限制為±5 V：a 1/4瓦，
PDD500A101使用流程120? 終端電阻器VIH/VIL差分模式：RS-422兼容差動輸入VIH：在主（正）輸入時發(fā)生電壓比壓差大100 mV共模內(nèi)的（負）輸入電壓電壓范圍為±25 V。VIL：在主（正）輸入時發(fā)生電壓比壓差小100 mV（負極）共模電壓范圍內(nèi)的輸入電壓±25 V。VIH/VIL單極（單端）模式（差分輸入連接到VTTL）：VIH=VTTL+100 mVVIL=VTTL-100 mV輸入滯后：50 mV輸入上升時間建議：最小上升時間-5 ns傳播延遲-25 ns典型值最大上升時間-1毫秒VMIVME-2540能夠接受不同的輸入在電壓和時域上有很大的優(yōu)勢。必須注意在以下情況下，確保輸入電壓在VTTL周圍穩(wěn)定：在單端模式下，將產(chǎn)生虛假數(shù)據(jù)。同樣，在使用差分輸入時，必須小心為確保輸入不允許隨相互之間或數(shù)據(jù)之間的電壓值在100 mV以內(nèi)可以生成轉(zhuǎn)換。
The Intelligent Counter/Controller supports two
VMEbus interrupter modules which may assert any of two
IRQ levels simultaneously. When serviced, the interrupter
modules respond with an 8-bit interrupt vector and
automatically clear the pending IRQ. The CPU maintains a
queue of pending interrupt events in memory, writing a new
IRQ to the interrupter modules when the previous event is
cleared.Common-Mode Voltage Limit: ±25 V
Differential Mode Voltage Limit: ±5 V
The differential voltage range is limited to ±5 V due to
a 1/4 W, 120 ? termination resistor
VIH/VIL Differential Mode: RS-422-compliant
differential input
VIH: Occurs whenever the primary (positive) input
voltage is 100 mV greater than the differential
(negative) input voltage within the common-mode
voltage range of ±25 V.
VIL: Occurs whenever the primary (positive) input
voltage is 100 mV less than the differential (negative)
input voltage within the common-mode voltage range
of ±25 V.
VIH/VIL Unipolar (Single-Ended) Mode
(Differential Input Connected to VTTL):
VIH = VTTL + 100 mV
VIL = VTTL - 100 mV
Input Hysteresis: 50 mV
Input Rise Time Recommendations:
Minimum rise time - 5 ns
Propagation delay - 25 ns typical
Maximum rise time - 1 msThe AM26LS33A differential receivers used on the
VMIVME-2540 are capable of accepting inputs that vary
greatly on voltage and time domain. Care must be taken to
ensure that the input voltages are stable around VTTL when
in single-ended mode or spurious data will be produced.
Similarly, when using differential inputs, care must be taken
to ensure that the inputs, are not allowed to float with
voltage values within 100 mV of each other or data
transitions may be generated.
