3BHE020356R0101使用書，ABB輸出模塊
由于8254僅存儲(chǔ)D7至D0上顯示的數(shù)據(jù)，因此兩個(gè)負(fù)載需要輸入完整的16位計(jì)數(shù)序列。這可以通過回顧表4.4.6-1。每個(gè)計(jì)數(shù)器寄存器必須加載兩次。第一個(gè)負(fù)載設(shè)置計(jì)數(shù)的最低有效字節(jié)，第二次加載設(shè)置最高有效字節(jié)伯爵夫人。對(duì)于每個(gè)計(jì)數(shù)器，必須先寫入控制字，然后寫入計(jì)數(shù)已寫入。4.4.7可編程間隔計(jì)時(shí)器編程順序表4.4.7-1給出了每個(gè)計(jì)數(shù)器寄存器的地址和要加載到每個(gè)寄存器的數(shù)據(jù)的描述。
3BHE020356R0101使用書審查第5.4.5節(jié)關(guān)于級(jí)聯(lián)計(jì)數(shù)器上的跳線安裝，最大計(jì)數(shù)器長(zhǎng)度為16、32、，或48位編程總線中斷器模塊（BIM）總線中斷模塊處理與CPU的所有中斷接口板可以在任何VMEbus級(jí)別（1到7）上生成中斷。當(dāng)BIM編程時(shí)，以及當(dāng)其中一個(gè)采用以下兩種ADC操作模式：隨機(jī)中斷模式和掃描中斷模式。
隨機(jī)中斷模式在完成單個(gè)a/D轉(zhuǎn)換。掃描中斷模式在完成2到64通道掃描時(shí)生成中斷。
當(dāng)上述中斷條件之一發(fā)生時(shí)，BIM生成一個(gè)VMEbus 1至7級(jí)中斷。必須事先啟用BIM中斷中斷電平必須事先編程，以便BIM運(yùn)行。4.4.9總線斷路器模塊（BIM）編程順序BIM只使用其四個(gè)中斷通道中的一個(gè)。因此，只有一個(gè)中斷控制寄存器（XX10）和一個(gè)中斷向量寄存器（XX18）需要進(jìn)行編程。每次中斷后，必須加載中斷控制寄存器為下一個(gè)中斷重新啟用。表4.4.9-1顯示了中斷控制和矢量寄存器位定義。然而，對(duì)于大多數(shù)應(yīng)用程序，在表4.4.9-2是正確中斷操作所需的全部?jī)?nèi)容。當(dāng)CPU板接受中斷時(shí)，它以中斷確認(rèn)周期。這是一種讀取循環(huán)，其中中斷設(shè)備（BIM）在數(shù)據(jù)位0至7上以8位中斷矢量響應(yīng)。對(duì)于680X0 CPU板，該向量乘以4并添加到向量基
Since the 8254 stores only the data presented on D7 to D0, two loads
are required to enter a full 16-bit count sequence. This can be seen by reviewing
Table 4.4.6-1. Each counter register must be loaded twice. The first load sets the
least significant byte of the count and the second load sets the most significant byte
of the count. For each counter the control word must be written first, then the count
is written.
4.4.7 Programmable Interval Timer Programming Sequence
Table 4.4.7-1 gives the address of each Counter Register and a
description of the data to load into each register. Review Section 5.4.5 concerning
jumper installation on cascading counters for maximum counter lengths of 16, 32,
or 48 bitsProgramming the Bus Interrupter Module (BIM)
The Bus Interrupt Module handles all interrupt interfacing to the CPU
board. An interrupt may be generated on any VMEbus level (1 through 7).
Interrupts are generated when the BIM is programmed to do so and when one of
the following two ADC operating modes are employed: RANDOM INTERRUPT
MODE and SCANNING INTERRUPT MODE.
The RANDOM INTERRUPT MODE generates an interrupt upon the
completion of a single A/D conversion. The SCANNING INTERRUPT MODE
generates an interrupt upon the completion of a 2- through 64-channel scan.
When one of the above interrupt conditions occurs, the BIM generates a
VMEbus level 1 through 7 interrupt. The BIM interrupt must be previously enabled
and the interrupt level must be previously programmed for the BIM to operate.
4.4.9 Bus Interrupter Module (BIM) Programming Sequence
The BIM uses only one of its four interrupt channels. Therefore, only one
Interrupt Control Register (XX10) and one Interrupt Vector Register (XX18) need to
be programmed. After each interrupt the Interrupt Control Register must be loaded
to re-enable for the next interrupt. Table 4.4.9-1 shows the Interrupt Control and
Vector Registers bit definitions. However, for most applications the bits defined in
Table 4.4.9-2 are all that are necessary for proper interrupt operation.
When an interrupt is accepted by the CPU board, it responds with an
Interrupt Acknowledge cycle. This is a type of read cycle in which the interrupting
device (the BIM) responds with an 8-bit Interrupt Vector on data bits 0 to 7. For a
680X0 CPU board, this vector is multiplied by four and added to the Vector Base
