2UBA002322R0001中文PDF用戶手冊，ABB模塊卡件
掃描中斷模式對輸入進(jìn)行單次掃描然后停止操作，與掃描輪詢模式相同。相反在狀態(tài)寄存器中設(shè)置標(biāo)志位時(shí)，會(huì)向總線生成一個(gè)信號中斷器模塊（68153），用于向CPU板生成VMEbus中斷。總線中斷器模塊（68153）必須事先編程為生成此VMEbus中斷，并在CPU板生成的中斷確認(rèn)周期。編程總線斷續(xù)器模塊（68153）詳見第4.4.7節(jié)。
2UBA002322R0001中文PDF用戶手冊掃描中斷模式可與用于執(zhí)行定期數(shù)據(jù)記錄的可編程定時(shí)器（8254）。要做到這一點(diǎn)如第4.4.6節(jié)所述，需要設(shè)置定時(shí)器和中斷器芯片通過4.4.9。CSR的控制字必須有位10（COUNT STARTH）設(shè)置而不是位13（EN START CONV H）。除了CPU低之外開銷，該模式將VMIVME-3112上的數(shù)字活動(dòng)最小化轉(zhuǎn)換。
要進(jìn)入掃描中斷模式，以下CSR位必須設(shè)置：隨機(jī)輪詢模式隨機(jī)輪詢模式是控制A/D轉(zhuǎn)換。CPU板寫入控制寄存器，選擇使用控制寄存器位MUX A5H到MUX A0H轉(zhuǎn)換的通道D5到D0）。然后，CPU必須設(shè)置EN START CONV H位（D13），該位啟動(dòng)多路復(fù)用器采集和ADC時(shí)序，詳見3.5節(jié)。然后，CPU必須輪詢狀態(tài)中的新數(shù)據(jù)RDY H位（D15）登記當(dāng)該標(biāo)志變高時(shí)，A/D轉(zhuǎn)換完成，數(shù)據(jù)已存儲(chǔ)在隨機(jī)轉(zhuǎn)換數(shù)據(jù)寄存器（RCDR）中。CPU然后，電路板讀取該數(shù)據(jù)并選擇下一個(gè)要轉(zhuǎn)換的通道。這當(dāng)需要轉(zhuǎn)換的通道不是按順序排列時(shí)，模式很有用，因此，可以按隨機(jī)順序選擇通道。在某些情況下，它也很有用頻道必須比其他頻道更頻繁地轉(zhuǎn)換。每次打開一個(gè)新頻道時(shí)選擇A/D轉(zhuǎn)換時(shí)，模式控制位必須設(shè)置為隨機(jī)位輪詢模式。必須設(shè)置以下CSR位：隨機(jī)中斷模式隨機(jī)中斷模式的操作與隨機(jī)中斷模式相同上述輪詢模式。唯一的區(qū)別是CPU收到的信號是A/D轉(zhuǎn)換由車載系統(tǒng)生成的VMEbus中斷完成總線斷續(xù)器模塊（68153）?？偩€中斷模塊必須編程在第一次轉(zhuǎn)換完成之前。然后在每次中斷后總線斷路器模塊必須通過一次負(fù)載操作重新啟用。提到第4.4.8節(jié)和第4.4.9節(jié)了解有關(guān)總線斷路器編程的更多信息單元每次選擇新通道進(jìn)行a/D轉(zhuǎn)換時(shí)，模式控制位必須設(shè)置為隨機(jī)中斷模式。以下CSR必須設(shè)置位：
The SCANNING INTERRUPT MODE performs a single scan of the input
channels, then stops operating, the same as the SCANNING POLL MODE. Instead
of setting a flag bit in the Status Register, a signal is generated to the Bus
Interrupter Module (68153) which generates a VMEbus Interrupt to the CPU board.
The Bus Interrupter Module (68153) must have previously been programmed to
generate this VMEbus Interrupt and also to respond with an 8-bit vector during the
Interrupt Acknowledge cycle generated by the CPU board. Programming of the
Bus Interrupter Module (68153) is detailed in Section 4.4.7.
The SCANNING INTERRUPT MODE can be used along with the
Programmable Timer (8254) to perform periodic data logging. To do this, it is
necessary to set up the timer and interrupter chips as described in Sections 4.4.6
through 4.4.9. The control word for the CSR must have bit 10 (COUNT STARTH)
set instead of bit 13 (EN START CONV H). In addition to having low CPU
overhead, this mode minimizes digital activity on the VMIVME-3112 during
conversions.
To enter the SCANNING INTERRUPT MODE the following CSR bits must
be set :
RANDOM POLLING MODE
The RANDOM POLLING MODE is the traditional method of controlling an
A/D conversion. The CPU board writes to the Control Register selecting the
channel to be converted using Control Registers bits MUX A5H through MUX A0H
(D5 through D0). The CPU must then set the EN START CONV H bit (D13), which
starts the multiplexer acquisition, and ADC timing sequence which was detailed in
Section 3.5. The CPU must then poll the NEW DATA RDY H bit (D15) in the Status
Register. When this flag goes high, the A/D conversion is complete and the data
has been stored in the Random Conversion Data Register (RCDR). The CPU
board then reads this data and selects the next channel to be converted. This
mode is useful when channels desired to be converted are not in sequential order,
thus channels can be selected in a Random order. It is also useful when some
channels must be converted more often than others. Each time a new channel is
selected for A/D Conversion, the Mode Control bits must be set to the RANDOM
POLLING MODE. The following CSR bits must be set: RANDOM INTERRUPT MODE
The RANDOM INTERRUPT MODE operates the same as the RANDOM
POLLING MODE described above. The only difference is that CPU is signaled that
the A/D conversion is complete by a VMEbus Interrupt generated by the on-board
Bus Interrupter Module (68153). The Bus Interrupt Module must be programmed
before the first conversion is completed. Then after each interrupt is serviced the
Bus Interrupter Module must be re-enabled by one load operation. Refer to
Sections 4.4.8 and 4.4.9 for more information on programming the Bus Interrupter
Module. Each time a new channel is selected for A/D conversion, the Mode
Control bits must be set to the RANDOM INTERRUPT MODE. The following CSR
bits must be set:
