GDC806A0101使用配置手冊,ABB模塊
個多路復(fù)用器接受八個差分輸入對。第二層多路復(fù)用器從八個輸入多路復(fù)用器中的一個接收所選通道。兩個多路復(fù)用器部分由同一組六個地址控制線路（INP MUX地址），從控制位“MUX A00”到控制寄存器中的“MUX A05”。3.6.2單端與差動操作模擬輸入的差分或單端操作通過以下方式選擇：單個串聯(lián)封裝（SIP）電阻器的位置，如所示圖3.6.1-1。輸入多路復(fù)用器始終在差分模式下工作；通過連接低輸入電阻至公共輸入接地感應(yīng)輸入，而不是至單個低信號輸入。
GDC806A0101使用配置手冊防止高頻噪聲成為共模信號并且使VMIVME-3112的數(shù)據(jù)輸出波動，輸入電路是單端制造，所有C行引腳均接地。這意味著所有示意圖中的RFILT電阻器SIP替換為SIP頭。這些是基本上為0? SIP電阻器。還安裝了跨接導(dǎo)線J2?，F(xiàn)在所有的輸入通過低電阻路徑將其回路連接到本地接地。這也改變了輸入濾波器的極點頻率，因為一半的輸入電阻消失了。新的頻率是微分值的兩倍。
所有VMIVME-3112輸入通道均由限流輸入電阻器進(jìn)行過電壓保護(hù)。輸入過電壓見第2節(jié)第2.3段規(guī)范。3.7跳線可編程增益放大器一旦選擇輸入通道并通過輸入通道布線多路復(fù)用器，它進(jìn)入可編程增益放大器作為差分輸入。這個差分放大器抑制共模噪聲，并向跟蹤保持（T&H）設(shè)備提供縮放單端輸出?？删幊淘鲆娣糯笃骺梢钥缃釉鲆鏋?、10、100、200和500。這允許-10 mV至+10 mV范圍內(nèi)的輸入將被放大至-5 V至+5 V輸入范圍用于ADC。當(dāng)選擇增益500時，CSR中的增益刪除位（D15）必須設(shè)置。這將模擬采集時間從15μs增加到28μs，以允許完成新通道的輸入設(shè)置。圖3.7-1顯示了增益可編程增益放大器的配置。
Each multiplexer accepts eight differential input pairs. A second tier
multiplexer receives the selected channel from one of the eight input multiplexers.
Both multiplexer sections are controlled by the same set of six address
lines (INP MUX ADDRESS), which are derived from control bits "MUX A00" through
"MUX A05" from the Control Register.
3.6.2 Single-Ended Versus Differential Operation
Differential or single-ended operation of the analog inputs is selected by
the location of single-in-line-package (SIP) resistors, as illustrated in
Figure 3.6.1-1. The input multiplexers are always operated in the differential mode; single-ended (pseudo-differential) operation is obtained by connecting the
LOW input resistor to the common INPUT GROUND SENSE input instead of to the
individual LOW signal inputs.
To prevent high frequency noise from becoming a common mode signal
and causing the data output of the VMIVME-3112 to fluctuate, the input circuits are
made single-ended and all of the row C pins are grounded. This means that all of
the RFILT resistor SIPs in the schematic are replaced with SIP headers. These are
essentially 0 ? SIP resistors. Jumper J2 is also installed. Now all of the inputs
have their returns tied to local ground via a low resistance path. This also shifts the
pole frequency of the input filter, since half of the input resistance is gone. The new
frequency is twice that of the differential value.
All VMIVME-3112 input channels are overvoltage protected by currentlimiting input resistors. See Section 2, paragraph 2.3 for input overvoltage
specifications.
3.7 JUMPER-PROGRAMMABLE GAIN AMPLIFIER
Once an input channel has been selected and routed through the input
multiplexers, it enters the Programmable Gain Amplifier as a differential input. The
differential amplifier rejects COMMON MODE noise and delivers a scaled singleended output to the Track-and-Hold (T&H) device. The Programmable Gain
Amplifier may be jumpered for gains of 1, 10, 100, 200, and 500. This allows for an
input in the -10 mV to +10 mV range to be scaled up to a -5 V to +5 V input range
for the ADC. When a gain of 500 is selected the GAIN DEL bit (D15) in the CSR
must be set. This increases the analog acquisition time from 15 μs to 28 μs to allow
complete input setting for the new channel. Figure 3.7-1 shows the gain
configuration for the Programmable Gain Amplifier.
