8521-TC-SA通用電氣卡件,GE使用流程
VMEbus系統(tǒng)重置? 信號7.Universe II ASIC（PCI/VME總線）的VMEbus重置源橋架控制器）：系統(tǒng)軟件重置和本地軟件重置下表顯示了受各種類型影響的設(shè)備重置次數(shù)。有關(guān)使用重置的詳細(xì)信息，請參閱MVME2600/2700系列單板計算機(jī)程序員參考指南。Endian問題PowerPC處理器和VMEbus本質(zhì)上是大端的，而PCI總線本質(zhì)上是小端的。
8521-TC-SA通用電氣卡件以下各節(jié)概述MVME2700如何處理Big和little endian操作中的軟件和硬件差異。有關(guān)endian注意事項的更多詳細(xì)信息，參考MVME2600/2700系列單板計算機(jī)程序員參考指南。處理器/內(nèi)存域MPC750處理器可以在大端和小端同時工作模式然而，它總是將外部處理器/內(nèi)存總線視為通過執(zhí)行地址重排和重新排序，在以little endian模式運(yùn)行。Raven MPU/PCI中的MPC寄存器總線橋控制器ASIC和Falcon內(nèi)存控制器芯片組以及DRAM、ROM/Flash和系統(tǒng)寄存器，始終顯示為大端詞。
Raven ASIC的作用由于PCI總線是little endian，Raven在中執(zhí)行字節(jié)交換從PCI到內(nèi)存和從處理器到PCI的兩個方向在編程以大端運(yùn)算時保持地址不變處理器和內(nèi)存子系統(tǒng)的模式。
在little endian模式下，Raven反向重新排列PCIbound訪問的地址，并重新排列內(nèi)存綁定訪的地址（來自PCI）。在這種情況下，不進(jìn)行字節(jié)交換。
PCI域PCI總線本質(zhì)上是小端的。所有直接連接到的設(shè)備PCI總線在little endian模式下運(yùn)行，而與處理器域中的操作。
PCI和SCSISCSI是面向字節(jié)流的；中地址最低的字節(jié)不管endian模式如何，內(nèi)存都是第一個要傳輸?shù)膬?nèi)存。由于Raven ASIC在兩個小端都保持地址不變性在大端模式下，SCSI數(shù)據(jù)不應(yīng)出現(xiàn)端位問題。Big-endian軟件仍然必須考慮字節(jié)交換效應(yīng)然而，當(dāng)訪問PCI/SCSI設(shè)備的寄存器時。
The VMEbus SYSRESET? signal
7. VMEbus Reset sources from the Universe II ASIC (PCI/VME bus
bridge controller): the System Software reset and Local Software
reset
The following table shows which devices are affected by the various types
of resets. For details on using resets, refer to the MVME2600/2700 Series
Single Board Computer Programmer’s Reference Guide.Endian Issues
The PowerPC processor and the VMEbus are inherently big-endian, while
the PCI bus is inherently little-endian. The following sections summarize
how the MVME2700 handles software and hardware differences in bigand little-endian operations. For further details on endian considerations,
refer to the MVME2600/2700 Series Single Board Computer
Programmer’s Reference Guide.Processor/Memory Domain
The MPC750 processor can operate in both big-endian and little-endian
mode. However, it always treats the external processor/memory bus as
big-endian by performing address rearrangement and reordering when
running in little-endian mode. The MPC registers in the Raven MPU/PCI
bus bridge controller ASIC and the Falcon memory controller chip set, as
well as DRAM, ROM/Flash, and system registers, always appear as
big-endian.
Role of the Raven ASIC
Because the PCI bus is little-endian, the Raven performs byte swapping in
both directions (from PCI to memory and from the processor to PCI) to
maintain address invariance while programmed to operate in big-endian
mode with the processor and the memory subsystem.
In little-endian mode, the Raven reverse-rearranges the address for PCIbound accesses and rearranges the address for memory-bound accesses
(from PCI). In this case, no byte swapping is done.
PCI Domain
The PCI bus is inherently little-endian. All devices connected directly to
the PCI bus operate in little-endian mode, regardless of the mode of
operation in the processor’s domain.
PCI and SCSI
SCSI is byte-stream-oriented; the byte having the lowest address in
memory is the first one to be transferred regardless of the endian mode.
Since the Raven ASIC maintains address invariance in both little-endian
and big-endian modes, no endian issues should arise for SCSI data.
Big-endian software must still take the byte-swapping effect into account
when accessing the registers of the PCI/SCSI device, however.
