HIER464920P0001培訓(xùn)教程,ABB模塊
? 計(jì)數(shù)器2為上的揚(yáng)聲器輸出功能提供音調(diào)PIB控制器（揚(yáng)聲器輸出信號，可通過電纜連接至通過遠(yuǎn)程重置連接器連接外部揚(yáng)聲器）。
間隔計(jì)時器使用OSC時鐘輸入作為其時鐘源。這個MVME2603/2604使用14.31818 MHz時鐘源驅(qū)動OSC引腳。16位定時器MVME2603/2604上有四個16位定時器。
HIER464920P0001培訓(xùn)教程PIB控制器提供一個16位定時器；Z8536 CIO設(shè)備提供其他三個。有關(guān)對這些計(jì)時器進(jìn)行編程的信息，請參閱數(shù)據(jù)W83C553 PIB控制器和Z8536 CIO設(shè)備的圖紙，如附錄D中列出了相關(guān)文件。
串行通信接口MVME2603/2604使用Zilog Z85230 ESCC（增強(qiáng)串行通信控制器）來實(shí)現(xiàn)兩個串行通信接口，通過P2路由。Z85230支持同步（SDLC/HDLC）和異步協(xié)議。這個MVME2603/2604硬件支持的異步串行波特率110B/s至38.4KB/s。
每個接口支持CT、DCD、RTS和DTR控制信號，如以及TxD和RxD發(fā)送/接收數(shù)據(jù)信號，以及TxC/RxC同步時鐘信號。因?yàn)椴⒎撬姓{(diào)制解調(diào)器控制線都可用在Z85230中，Z8536 CIO用于提供缺失的調(diào)制解調(diào)器線路。PAL設(shè)備執(zhí)行寄存器訪問和偽中斷的解碼在ISA輸入/輸出空間中確認(rèn)Z85230和Z8536的周期。這個PIB控制器為Z85230提供DMA支持。
Z85230接收10MHz時鐘輸入。Z85230提供偽中斷確認(rèn)周期期間的中斷向量。向量是根據(jù)中斷源在Z85230內(nèi)修改。打斷請求級別通過PIB控制器編程。參見Z85230數(shù)據(jù)表和MVME2603/MVME2604程序員參考指南，均列于附錄D相關(guān)文件中，以供進(jìn)一步了解信息
? Counter 2 provides the tone for the speaker output function on the PIB controller (the SPEAKER_OUT signal which can be cabled to an external speaker via the remote reset connector). The interval timers use the OSC clock input as their clock source. The MVME2603/2604 drives the OSC pin with a 14.31818 MHz clock source. 16-Bit Timers Four 16-bit timers are available on the MVME2603/2604. The PIB controller supplies one 16-bit timer; the Z8536 CIO device provides the other three. For information on programming these timers, refer to the data sheets for the W83C553 PIB controller and the Z8536 CIO device, as listed in Appendix D, Related Documentation. Serial Communications Interface The MVME2603/2604 uses a Zilog Z85230 ESCC (Enhanced Serial Communications Controller) to implement the two serial communications interfaces, which are routed through P2. The Z85230 supports synchronous (SDLC/HDLC) and asynchronous protocols. The MVME2603/2604 hardware supports asynchronous serial baud rates of 110B/s to 38.4KB/s. Each interface supports the CTS, DCD, RTS, and DTR control signals as well as the TxD and RxD transmit/receive data signals, and TxC/RxC synchronous clock signals. Since not all modem control lines are available in the Z85230, a Z8536 CIO is used to provide the missing modem lines. A PAL device performs decoding of register accesses and pseudo interrupt acknowledge cycles for the Z85230 and the Z8536 in ISA I/O space. The PIB controller supplies DMA support for the Z85230. The Z85230 receives a 10MHz clock input. The Z85230 supplies an interrupt vector during pseudo interrupt acknowledge cycles. The vector is modified within the Z85230 according to the interrupt source. Interrupt request levels are programmed via the PIB controller. Refer to the Z85230 data sheet and to the MVME2603/ MVME2604 Programmer’s Reference Guide, both listed in Appendix D, Related Documentation, for further information.
