HIEE400106R0001模塊,ABB產(chǎn)品尺寸
由PIB中的端口92寄存器控制的功能（當(dāng)MVME2603/2604為系統(tǒng)時(shí)，重置VMEbus控制器）
5、由時(shí)鐘除數(shù)寄存器控制的PCI/ISA輸入/輸出復(fù)位功能在PIB中6.VMEbus系統(tǒng)重置? 信號(hào)
7.Universe ASIC（PCI/VME總線）的VMEbus重置源橋架控制器）：系統(tǒng)軟件重置和本地軟件重置。下表顯示了受各種類型影響的設(shè)備重置次數(shù)。
HIEE400106R0001模塊有關(guān)使用重置的詳細(xì)信息，請(qǐng)參閱MVME2600系列單附錄D中列出的Board Computer Programmer參考指南，相關(guān)文檔Endian問題MVME2603/2604支持兩種little endian（例如，Windows NT）和big-endian（例如AIX）軟件。PowerPC處理器和VMEbus本身就是big-endian，而PCI總線是big-endian天生的小端。以下各節(jié)總結(jié)了MVME2603/2604處理大型和小型計(jì)算機(jī)中的軟件和硬件差異小端運(yùn)算。有關(guān)endian注意事項(xiàng)的更多詳細(xì)信息，請(qǐng)參閱MVME2600系列單板計(jì)算機(jī)程序員參考指南，見附錄D，相關(guān)文件。處理器/內(nèi)存域MPC603/604處理器可以在大端和小端模式。然而，它總是處理外部通過執(zhí)行地址將處理器/內(nèi)存總線作為大端在小端模式下運(yùn)行時(shí)重新排列和排序。這個(gè)Raven MPU/PCI總線網(wǎng)橋控制器ASIC和Falcon內(nèi)存控制器芯片組，以及DRAM、ROM/Flash和系統(tǒng)寄存器，始終顯示為大端。Raven ASIC的作用由于PCI總線是little endian，Raven在中執(zhí)行字節(jié)交換從PCI到內(nèi)存和從處理器到PCI的兩個(gè)方向在編程以大端運(yùn)算時(shí)保持地址不變處理器和內(nèi)存子系統(tǒng)的模式。在little endian模式下，Raven反向重新排列PCIbound訪問的地址，并重新排列內(nèi)存綁定訪問的地址（來自PCI）。在這種情況下，不進(jìn)行字節(jié)交換。PCI域PCI總線本質(zhì)上是小端的。所有直接連接到的設(shè)備PCI總線在little endian模式下運(yùn)行，而與處理器域中的操作。
ALT_RST? function controlled by the Port 92 register in the PIB
(resets the VMEbus when the MVME2603/2604 is system
controller)
5. PCI/ISA I/O Reset function controlled by the Clock Divisor register
in the PIB
6. The VMEbus SYSRESET? signal
7. VMEbus Reset sources from the Universe ASIC (PCI/VME bus
bridge controller): the System Software reset and Local Software
Reset.
The following table shows which devices are affected by the various types
of resets. For details on using resets, refer to the MVME2600 Series Single
Board Computer Programmer’s Reference Guide, listed in Appendix D,
Related DocumentationEndian Issues
The MVME2603/2604 supports both little-endian (for example,
Windows NT) and big-endian (for example, AIX) software. The PowerPC
processor and the VMEbus are inherently big-endian, while the PCI bus is
inherently little-endian. The following sections summarize how the
MVME2603/2604 handles software and hardware differences in big- and
little-endian operations. For further details on endian considerations, refer
to the MVME2600 Series Single Board Computer Programmer’s
Reference Guide, listed in Appendix D, Related Documentation.
Processor/Memory Domain
The MPC603/604 processor can operate in both big-endian and
little-endian mode. However, it always treats the external
processor/memory bus as big-endian by performing address
rearrangement and reordering when running in little-endian mode. The
MPC registers in the Raven MPU/PCI bus bridge controller ASIC and the
Falcon memory controller chip set, as well as DRAM, ROM/Flash, and
system registers, always appear as big-endian.
Role of the Raven ASIC
Because the PCI bus is little-endian, the Raven performs byte swapping in
both directions (from PCI to memory and from the processor to PCI) to
maintain address invariance while programmed to operate in big-endian
mode with the processor and the memory subsystem.
In little-endian mode, the Raven reverse-rearranges the address for PCIbound accesses and rearranges the address for memory-bound accesses
(from PCI). In this case, no byte swapping is done.
PCI Domain
The PCI bus is inherently little-endian. All devices connected directly to
the PCI bus operate in little-endian mode, regardless of the mode of
operation in the processor’s domain.
